onbreak {resume}
transcript on

set PrefMain(saveLines) 50000
.main clear

if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

# load designs

# insert files specific to your design here

vlog -sv -work rtl_work +define+SIMULATION SRAM_Controller.v
vlog -sv -work rtl_work tb_SRAM_Emulator.v
vlog -sv -work rtl_work Clock_100_PLL.v
vlog -sv -work rtl_work DP_RAM0.v
vlog -sv -work rtl_work DP_RAM1.v
vlog -sv -work rtl_work SWrite.v
vlog -sv -work rtl_work tb_SWrite.v

# specify library for simulation
vsim -t 100ps -L altera_mf_ver -lib rtl_work tb_SWrite

# Clear previous simulation
restart -f

view wave
add wave Clock_50

######################################################
# SPLoad
######################################################
add wave uut/resetn
add wave uut/start
add wave uut/finish
add wave uut/state
# DP_RAM
add wave -hexadecimal uut/DP_Addr
add wave -hexadecimal uut/DP_Read
add wave -hexadecimal uut/DP_Write
add wave -hexadecimal uut/DP_we
# SRAM
add wave -hexadecimal uut/SRAM_Addr
add wave -hexadecimal uut/SRAM_Read
add wave -hexadecimal uut/SRAM_Write
add wave uut/SRAM_we
# Intermediate variables
add wave -hexadecimal uut/DP_ReadClipped
add wave -hexadecimal uut/baseOffset
add wave -unsigned uut/row
add wave -unsigned uut/col

# run complete simulation
run -all

destroy .structure
destroy .signals
destroy .source

simstats
